1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same semiconductor device, and more specifically to a semiconductor device having a capacitor and MIS transistors and a method of manufacturing the same.
2. Description of the Prior Art
FIGS. 18 to 22 show a prior art method of manufacturing a semiconductor device having a capacitor and MCS transistors. Here, however, the prior art manufacturing method as shown in these drawings is known by the Inventors in private, and therefore this prior art manufacturing method is not a prior art well known in public.
In FIG. 22, a capacitor Cap shown on the right side of the same drawing is a thin film condenser widely used an integrated condenser of an analog integrated circuit. This capacitor Cap is composed of an upper electrode UE, a lower electrode LE, and a dielectric film 35 sandwiched between the two electrodes UE and LE. In the semiconductor device having a capacitor Cap as described above, in order to reduce the number of the manufacturing steps and the number of the semiconductor layers, the lower electrode LE of the capacitor of two-layer structure and a gate electrode G of a MOS transistor of the same two-layer structure as shown on the left side of the same drawing are generally formed by use of two common layers. Further the upper electrode UE of the capacitor and some electrode wires 44 of the MOS transistor are generally formed by use of two common layers.
Here, the method of manufacturing the semiconductor device having the capacitor Cap as described above will be described hereinbelow briefly with reference to FIGS. 18 to 22.
First, as shown in FIG. 18, a p-well 12, an n-well 14 and an n-well 16 are formed on the surface of a silicon substrate 10. Furthers a plurality of element separating regions 20 are formed on the same surface of the substrate 10. On the left side in FIG. 18, an N-MOS transistor and a P-MOS transistor are formed at a portion sandwiched between the two element separating regions 20, respectively. Further, on the right side of FIG. 18, a capacitor Cap is formed on the element separating region 20 formed on the n-well 16. Here, since the structure of both the N-MOS transistor and the P-MOS transistor is basically the same with respect to each other, except the sort of its impurity type, only the N-MOS transistor will be mainly explained hereinbelow.
In the N-MOS transistor 12, an ohmic contact region 21, a source diffusion layer S, and a drain diffusion layer D are formed between the two element separating regions 20, respectively. This ohmic contact region 21 is formed to apply a voltage to the p-well 12. Further, a gate insulating film I is formed on a channel formed between the source diffusion layer S and the drain diffusion layer D. Further, a poly silicon Poly is formed on this gate insulating film I as a part of the gate electrode G. The gate electrode G is formed as a two-layer structure of the poly silicon Poly and a silicide film 22 (described later). The same process as explained above can be applied to the P-MOS transistor.
When the poly silicon Poly of the gate electrode G is formed, a poly silicon layer 30 is necessarily formed as the same layer, as shown on the right side in the same drawing. In other words, the lower electrode LE of the capacitor is formed as a two-layer structure of the poly silicon layer 30 and the silicide film 32 (described later).
Further, a high melting point metal film formed of Co (Cobalt) is formed on the ohmic contact region 21, the source diffusion region S, the drain diffusion region D, the poly silicon Poly, and the poly silicon layer 30. After that, silicide film pieces 22 and 32 formed of CoSi.sub.2 are selectively formed through a silicide process for performing selective etching on the basis of reaction between the high melting point metal film and the poly silicon layer, respectively. The silicide films 22 and 32 are formed to reduce the resistances of the gate electrode G formed mainly of poly silicon and the lower electrode LE of the capacitor Cap, respectively. The above-mentioned process has been well known, so that more detailed description thereof is omitted herein.
Further, a SiO.sub.2 film 24 is formed all over the surface thereof by low pressure CVD (chemical vapor deposition) method. Further, the formed SiO.sub.2 film 24 is etched by photo-lithography and RIE (reactive ion etching) to form a hole 31. By this process, it is possible to expose the silicide film 32 at a region in which the capacitor Cap is to be formed. In accordance with the above-mentioned process, an intermediate semiconductor device as shown in FIG. 18 can be obtained.
Further, as understood by FIG. 19, a Si.sub.3 N.sub.4 layer 35A is formed all over the surface of the semiconductor device, that is, all over the SiO.sub.2 film 24 formed as a cover and the silicide film 32 formed as a bottom of the hole 31 by an LPCVD (low pressure CVD) method.
Further, a part of the Si.sub.3 N.sub.4 layer 35A is removed by photo-lithography and RIE, to leave the same layer 35A as a capacitor dielectric film 35. On the basis of the above-mentioned process, it is possible to obtain the intermediate semiconductor device as shown in FIG. 19. Further, as described above, when the Si.sub.3 N.sub.4 layer 35A is removed by the RIE, since the silicide film pieces 22 formed on the ohmic contact region 21, the source diffusion layer S, and the drain diffusion layer D can be protected by the SiO.sub.2 film 24, the silicide film pieces 22 are not damaged.
Further, as understood by FIG. 20, the SiO.sub.2 film 24 is etched by the photo-lithography and RIE, to form some contact holes 26, so that it is possible to expose the silicide film pieces 22 at the bottoms of these formed contact holes 26. On the basis of the above-mentioned process, it is possible to obtain an intermediate semiconductor device as shown in FIG. 20. Further, although a hole reaching the gate electrode G has been formed, this gate electrode G is formed at a position not seen by the cross-sectional view shown in FIG. 20.
Further, as understood by FIG. 21, as pre-process of forming a barrier metal layer 40 and a wiring layer 42 (both described later), all over the surface of the intermediate semiconductor device is cleaned. In more detail, a reverse spattering processing is performed by etching the uppermost surface of the semiconductor device, while applying a voltage to the silicon substrate 10. Further, the barrier metal layer 40 formed of TiN and the wiring layer 42 formed of Al are formed both by spattering. By this process, it is possible to obtain an intermediate semiconductor device as shown in FIG. 21.
Further, as understood by FIG. 22, the barrier metal layer 40 and the wiring layer 42 are both patterned or etched by the photo-lithography and RIE, to form electrode wires 44 of both the N-type and P-type MOS transistors and the upper electrode UE of the capacitor Cap. By this process, it is possible to obtain an intermediate semiconductor device as shown in FIG. 22. On the basis of the above-mentioned process, although the wiring at the lowermost layer can be completed, it is of course necessary to put other wiring layers one upon another where necessary.
As described above, in the prior art manufacturing method, in order to reduce the contact resistance between the electrode wire 44 and each of the gate electrode G, the source diffusion electrode layer S and the drain diffusion layer D, respectively, as the pre-process of forming the barrier metal layer 40 and the wiring layer 42, the cleaning process is needed. In other words, it has been necessary to remove the high resistance oxide layer inevitably formed on the surfaces of the silicide film 22. In the intermediate semiconductor device sa shown in FIG. 20, however, since the silicide film pieces 22 are formed on the surfaces of the ohmic contact region 21, the source diffusion electrode layer S, the drain diffusion layer D and the gate electrode G, respectively, it has been impossible to perform the above-mentioned cleaning and HF (hydrofluoric acid) processing. That is, when the intermediate semiconductor device is cleaned by use of pure hydrofluoric acid, there exists a problem in that not only the high resistance oxide substance formed on the surface side thereof but also the silicide film pieces 22 are all etched. Therefore, as already explained, the uppermost surface of the semiconductor device has been so far etched by applying a voltage to the substrate, that is, by the method of the reverse spattering processing.
In this case, however, since the capacitor dielectric film 35 is inevitably damaged by this etching processing (cleaning processing), the insulation of the capacitor Cap degrades and thereby the long-term reliability of the semiconductor device also deteriorates. In other words, since the surface of the capacitor dielectric film 35 as shown in FIG. 20 is damaged by the etching process, a space between the lower electrode LE and the upper electrode UE of the capacitor Cap varies partially, with the result that there exists a problem in that the capacitance and the breakdown voltage of the capacitor Cap cannot be both uniformalized.